Can we Case statement in this scenerio?
if (cmd==1'b1) && (f_addr==16'h1111) begin
......end
if (cmd==1'b0) begin
... end
else if (cmd ==1'b1) begin
.... end
Thanks very much
In reply to jennra:
case(1)
(cmd==1'b1) && (f_addr==16'h1111):
begin
... end
(cmd==1'b0):
begin
... end
(cmd ==1'b1):
begin
... end
endcase
In SystemVerilog, you can use the qualifier
priority case to assert that you always have a matching case item.
In reply to dave_59:
Thanks very much for your help
In reply to jennra:
Hi Dave
Just someclarification on this
what does case(1) means here??
Many thanks
In reply to jennra:
1, or more specifically 1’b1 is the result of a true Boolean expressions. The case statement executes the first case item that matches the case(expression).
In reply to dave_59:
I am trying to build async accumulator could you please let me know what is going wrong?
module async_accum#(
parameter DEPTH = 3
)(
input logic en[DEPTH],
input logic [3:0] inc[DEPTH],
output int result
);
always@(en[0] or en[1] or en[2]) begin
case({en[2], en[1], en[0]})
000: begin
result = result;
end
001: begin
result += inc[0];
end
010: begin
result += inc[1];
end
100: begin
result += inc[2];
end
011: begin
result += inc[0];
result += inc[1];
end
101: begin
result += inc[0];
result += inc[2];
end
110: begin
result += inc[1];
result += inc[2];
end
111: begin
result += inc[0];
result += inc[1];
result += inc[2];
end
default: begin
result = 0;
end
endcase
end
endmodule
module async_accum_tb;
parameter DEPTH = 3;
logic en[DEPTH];
logic [3:0] inc[DEPTH];
int result;
int result_exp;
logic enable[DEPTH];
logic pass_fail;
int i,j,k,l,cnt;
logic init;
async_accum#(
.DEPTH(DEPTH)
)(
.*
);
initial begin
$dumpfile(“dump.vcd”);
$dumpvars;
cnt = 10;
{i,j,k,l,init} = 'h0;
write(!init, en, inc);
check(!init,en, inc, result, result_exp, pass_fail);
repeat(cnt) begin
#1;
write(init, en, inc);
check(init, en, inc, result, result_exp, pass_fail);
end
end
task check(input init, input enable_c[DEPTH], input logic [3:0] inc_c[DEPTH], input int result_a, output int result_e, output logic pass_fail_c);
logic en_c0;
logic en_c1;
logic en_c2;
logic [3:0] in_c0;
logic [3:0] in_c1;
logic [3:0] in_c2;
i=0;
repeat(DEPTH) begin
en_c0 = enable_c[0];
en_c1 = enable_c[1];
en_c2 = enable_c[2];
in_c0 = inc_c[0];
in_c1 = inc_c[1];
in_c2 = inc_c[2];
result_e = enable_c[i]? result_e + inc_c[i]: result_e;
$display("time is %0d result is %0h {en[2],en[1],en[0]} is %0h inc[2] is %0h inc[1] is %0h inc[0] is %0h ",$time, result, {en[2], en[1], en[0]} , inc[2], inc[1], inc[0]);
i++;
end
if(((result_a !== result_e) && init) || ((result_a != result_e) && !init)) begin
$display(“fail result_act is %d result_exp is %d”, result_a, result_e);
end
endtask
task write(input logic init_w, output logic enable_l[DEPTH], output logic [3:0] incr_l[DEPTH]);
i=0;
repeat(DEPTH) begin
if(init_w) begin
enable_l[i] = 'hx;
incr_l[i][3:0] = 'hx;
end else begin
enable_l[i] = $urandom();
incr_l[i][3:0] = $urandom();
end
i++;
end
endtask
endmodule
time is 0 result is 0 {en[2],en[1],en[0]} is x inc[2] is x inc[1] is x inc[0] is x
time is 0 result is 0 {en[2],en[1],en[0]} is x inc[2] is x inc[1] is x inc[0] is x
time is 0 result is 0 {en[2],en[1],en[0]} is x inc[2] is x inc[1] is x inc[0] is x
time is 1 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is f inc[1] is 2 inc[0] is c
time is 1 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is f inc[1] is 2 inc[0] is c
time is 1 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is f inc[1] is 2 inc[0] is c
fail result_act is 0 result_exp is 17
time is 2 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is a inc[1] is b inc[0] is 7
time is 2 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is a inc[1] is b inc[0] is 7
time is 2 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is a inc[1] is b inc[0] is 7
fail result_act is 0 result_exp is 27
time is 3 result is 0 {en[2],en[1],en[0]} is 2 inc[2] is 1 inc[1] is 2 inc[0] is 5
time is 3 result is 0 {en[2],en[1],en[0]} is 2 inc[2] is 1 inc[1] is 2 inc[0] is 5
time is 3 result is 0 {en[2],en[1],en[0]} is 2 inc[2] is 1 inc[1] is 2 inc[0] is 5
fail result_act is 0 result_exp is 29
time is 4 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is 4 inc[1] is f inc[0] is a
time is 4 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is 4 inc[1] is f inc[0] is a
time is 4 result is 0 {en[2],en[1],en[0]} is 4 inc[2] is 4 inc[1] is f inc[0] is a
fail result_act is 0 result_exp is 33
time is 5 result is 0 {en[2],en[1],en[0]} is 3 inc[2] is 5 inc[1] is c inc[0] is 8
time is 5 result is 0 {en[2],en[1],en[0]} is 3 inc[2] is 5 inc[1] is c inc[0] is 8
time is 5 result is 0 {en[2],en[1],en[0]} is 3 inc[2] is 5 inc[1] is c inc[0] is 8
fail result_act is 0 result_exp is 53
time is 6 result is 0 {en[2],en[1],en[0]} is 1 inc[2] is f inc[1] is 7 inc[0] is c
time is 6 result is 0 {en[2],en[1],en[0]} is 1 inc[2] is f inc[1] is 7 inc[0] is c
time is 6 result is 0 {en[2],en[1],en[0]} is 1 inc[2] is f inc[1] is 7 inc[0] is c
fail result_act is 0 result_exp is 65
time is 7 result is c {en[2],en[1],en[0]} is 0 inc[2] is 1 inc[1] is 9 inc[0] is 2
time is 7 result is c {en[2],en[1],en[0]} is 0 inc[2] is 1 inc[1] is 9 inc[0] is 2
time is 7 result is c {en[2],en[1],en[0]} is 0 inc[2] is 1 inc[1] is 9 inc[0] is 2
fail result_act is 12 result_exp is 65
time is 8 result is c {en[2],en[1],en[0]} is 5 inc[2] is 7 inc[1] is f inc[0] is 2
time is 8 result is c {en[2],en[1],en[0]} is 5 inc[2] is 7 inc[1] is f inc[0] is 2
time is 8 result is c {en[2],en[1],en[0]} is 5 inc[2] is 7 inc[1] is f inc[0] is 2
fail result_act is 12 result_exp is 74
time is 9 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 6 inc[1] is 1 inc[0] is 8
time is 9 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 6 inc[1] is 1 inc[0] is 8
time is 9 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 6 inc[1] is 1 inc[0] is 8
fail result_act is 0 result_exp is 81
time is 10 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 2 inc[1] is 0 inc[0] is 9
time is 10 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 2 inc[1] is 0 inc[0] is 9
time is 10 result is 0 {en[2],en[1],en[0]} is 6 inc[2] is 2 inc[1] is 0 inc[0] is 9
fail result_act is 0 result_exp is 83