Case statement in verilog/SV

SystemVerilog
2

In reply to jennra:

case(1)
(cmd==1'b1) && (f_addr==16'h1111):
    begin
... end
(cmd==1'b0):
    begin
... end
(cmd ==1'b1):
    begin
... end
endcase

In SystemVerilog, you can use the qualifier
priority case to assert that you always have a matching case item.