Can any kind of display statement be used within property endpropert

SystemVerilog
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1

Hi all,

I’m trying assertions
this is the code -

property p1;
   @(posedge core_clk)	$fell(g1) |-> ($rose(g3) throughout $fell(g4)) ##80 $rose(g5);
   //`uvm_info("ASSERTION","INSIDE ASSERTION MODULE",UVM_MEDIUM)
endproperty

this assertion is passing(as I dont see any errors in simulation.log), but for my double-confirmation I wanted to display some statement to know if this part of assertion is working

for the `uvm_info I’m using I’m getting error as -

Error-[UM] Undefined macro
 Undefined macro exists as: 'uvm_info'
 token is '`uvm_info'
     `uvm_info("ASSERTION","INSIDE ASSERTION MODULE",UVM_MEDIUM)

I’ve imported the uvm_pkg as well in the same file
Is there any way to add statement to check my requirement?

2

In reply to Annapoornahm:

The above error is most likely due to the missing include of uvm_macros.svh file. Now, on your Q of Property/SVA debug, yes, quoting an example from a recent post:


assert property( ab ) $display("T:%0t Pass",$time);
 
                  else $display("T:%0t Fails",$time);

Replace $display with uvm_info as you wish (BTW adding a Pass action block is a really bad idea, instead, use your tool’s options to print stats at the end).

Also, you can do seq-matching feature to print messages in a longer, temporal SVA as well.

Good luck

3

In reply to Annapoornahm:

System task like $display is used along with a sequence expression.


property p1;
 ( $rose(req), $display("req received at time:%0t",$time)) |=> ($rose(grant)[->1], $display("grant received at time:%0t",$time));
endproperty

Note: The $display() executes only if the sequence matches

One can also use 1 ( always true ) as a sequence expression


property p2;
 $rose(req) ##0 (1,$display("req received at time:%0t",$time)) |=> $rose(grant)[->1] ##0( 1,$display("grant received at time:%0t",$time));
endproperty

Try the following:


property p1;
@(posedge core_clk) $fell(g1) |-> ($rose(g3) throughout $fell(g4)) ##80 $rose(g5)
 ##0(1,`uvm_info("ASSERTION","INSIDE ASSERTION MODULE",UVM_MEDIUM) );
endproperty

Personally I have never tried `uvm_info as sequence_match_item ( although I have tried them as pass action block ).

Let us know if it works ( I assume you have `include uvm_macros.svh,uvm_pkg.svh and then imported the uvm_pkg )

4

In reply to MICRO_91:

Turns out the expansion of macro `uvm_info prohibits its use as sequence_match_item.
( The macro internally calls function ‘uvm_report_info’ in class uvm_report_object which then calls function ‘report’ in class uvm_report_handler )

Try the following which works:


function void disp();
  `uvm_info("ASSERTION","INSIDE ASSERTION MODULE",UVM_MEDIUM)
endfunction

property p1;
  @(posedge core_clk) $fell(g1) |-> ($rose(g3) throughout $fell(g4)) ##80 $rose(g5) ##0(1,disp()); 
// disp() can also be attached to sequence $rose(g5). Eg: ... ##80 ($rose(g5),disp() )
endproperty

To re-use function ‘disp’ for different messages, add the respective 3 argument type of `uvm_info to ‘disp’

5

In reply to MICRO_91:

Yes @MICRO_91 both your methods worked for displaying statements.
Thank you