Can any kind of display statement be used within property endpropert

SystemVerilog
, , ,
2

In reply to Annapoornahm:

The above error is most likely due to the missing include of uvm_macros.svh file. Now, on your Q of Property/SVA debug, yes, quoting an example from a recent post:


assert property( ab ) $display("T:%0t Pass",$time);
 
                  else $display("T:%0t Fails",$time);

Replace $display with uvm_info as you wish (BTW adding a Pass action block is a really bad idea, instead, use your tool’s options to print stats at the end).

Also, you can do seq-matching feature to print messages in a longer, temporal SVA as well.

Good luck