Can any kind of display statement be used within property endpropert

SystemVerilog
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4

In reply to MICRO_91:

Turns out the expansion of macro `uvm_info prohibits its use as sequence_match_item.
( The macro internally calls function ‘uvm_report_info’ in class uvm_report_object which then calls function ‘report’ in class uvm_report_handler )

Try the following which works:


function void disp();
  `uvm_info("ASSERTION","INSIDE ASSERTION MODULE",UVM_MEDIUM)
endfunction

property p1;
  @(posedge core_clk) $fell(g1) |-> ($rose(g3) throughout $fell(g4)) ##80 $rose(g5) ##0(1,disp()); 
// disp() can also be attached to sequence $rose(g5). Eg: ... ##80 ($rose(g5),disp() )
endproperty

To re-use function ‘disp’ for different messages, add the respective 3 argument type of `uvm_info to ‘disp’