How to write an Assertion for a clock less than or equal to 1250MHz
CLK <= 1250MHZ and clock CLK will be less than or equal to another clock2 . considering as CLK2
can you please help for this assertion
CLK <= 1250 MHZ and CLK <= CLK2
In reply to srikanth.verification:
Attached is my code per a somewhat understanding of your requirements.
With the +10ps I was getting some passes and fails because of the accuracy issues in dealing with real numbers. Adjust the code as you see fit.
module top;
timeunit 1ns; timeprecision 100ps;
`include "uvm_macros.svh" import uvm_pkg::*;
bit clk1250, clk;
let period1250= 0.8ns;
initial forever #0.4 clk1250 = !clk1250;
initial forever #0.5 clk=!clk;
/*How to write an Assertion for a clock less than or equal to 1250MHz
CLK <= 1250MHZ and clock CLK will be less than or equal to another clock2 . considering as CLK2
can you please help for this assertion
CLK <= 1250 MHZ and CLK <= CLK2
clk <= 1250 meaning clk period is greater or equal to 0.8ns
clk <= clk2 meaning clk period is greater than period of 1250MHZ*/
property p_periods;
realtime v1250, vclk, vprd1250, vprd; // times ad periods for clsk1250 and clk
@(posedge clk1250) (1, v1250=$realtime) ##1 (1, vprd1250=$realtime-v1250) ##0
@(posedge clk) (1, vclk=$realtime) ##1 (1, vprd=$realtime-vclk) ##0
vprd1250 >=period1250-10ps && vprd >= period1250 + 10ps;
endproperty
ap_periods: assert property(@ (posedge clk) p_periods);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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