Assertion for check SOP signal loss

SystemVerilog
,
2

In reply to DefaultName:
Your approach looks OK, but I took a different approach with support logic that addresses other cases. specifically, i address the following requirements

  1. if(eop) then an sop has happened
  2. Every sop has its own eop
  3. After an sop no new sop until an eop

See my paper on support logic, the link is in my signature below.


module top;
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    bit clk, sop, eop, sop_happen;
    int sop_count, eop_count;
    default clocking @(posedge clk);
    endclocking
    initial forever #10 clk = !clk;
    // Support logic to detect the occurence of a sop 
    always @(posedge clk) begin
       if(sop) sop_happen<=1'b1; 
       if(eop & !sop) sop_happen <= 1'b0;
    end
    // if an eop then sop happened in the past 
    ap_eop_with_sop: assert property(eop |-> sop_happen==1);
    // **********
    // Functions to maintain the counts of sop, eop 
    function void inc_sop();
        sop_count=sop_count+1;
    endfunction: inc_sop
    
    function void inc_eop();
        eop_count=eop_count+1;
    endfunction: inc_eop
    // Every sop has its own eop 
    property p_sop_eop; 
      int sop_flag;
        (sop, sop_flag=sop_count, inc_sop()) |=> eop[->1] ##0 eop_count==sop_flag;
    endproperty
    // Pass or fail, the eop count is incremented 
    ap_sop_eop: assert property(p_sop_eop) inc_eop(); else inc_eop(); 

    initial begin
      bit v_a, v_b, v_err;
      repeat (200) begin
        @(posedge clk);
        if (!randomize(
                v_a, v_b, v_err
            ) with {
              v_a dist {
                1'b1 := 1,
                1'b0 := 1
              };
              v_b dist {
                1'b1 := 1,
                1'b0 := 2
              };
              v_err dist {
                1'b1 := 1,
                1'b0 := 15
              };
            })
          `uvm_error("MYERR", "This is a randomize error");
        sop <= v_a;
        if (v_err == 0) eop <= v_b;
        else eop <= !v_b;
      end
      $finish;
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books:
  1. Papers:
    Understanding the SVA Engine,
    Verification Horizons
    Reflections on Users’ Experiences with SVA, part 1
    Reflections on Users’ Experiences with SVA
    Reflections on Users’ Experiences with SVA, part 2
    Reflections on Users’ Experiences with SVA - Part II
    SUPPORT LOGIC AND THE ALWAYS PROPERTY
    http://systemverilog.us/vf/support_logic_always.pdf
    SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
    SVA in a UVM Class-based Environment
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    SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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