Assertion failing - no clue why!

In reply to somys:
You need to clearly write your requirements in English.
It sounds like what you want is that for every associated data_valid && src_port pair
data_valid==0 until ($rose(signal_sop) && src_port==id)[->1].

Is this what you want?
See if this will work:

 

 first_match(
     (!data_valid && src_port==id ##[0:$]src_port!=id) [*0:$] ##1 
      $rose(signal_sop) && src_port==id
             );

Ben Ben@systemverilog.us