In reply to ben@SystemVerilog.us:
In reply to somys:
You error is in the location of the “!” operator
You have:
(!(data_valid & (src_port==id))) throughout ( (($rose(signal_sop)) && (src_port == id))[->1] );
Should be:
(!data_valid && src_port==id) throughout ($rose(signal_sop) && src_port==id)[->1];
Thanks a lot for replying.
In my case, the src_port can be different than “id” at times and for those id’s, data valid is allowed to be 1 after $rose(signal_eop) is seen for a specific ID. data valid should be 0 until $rose(signal_sop) is seen for that same ID.
Doesn’t your solution require data_valid=0 and src_port==id all the time? and not allow src_port to be any different than that specific ID?
please explain since I am at loss with this understanding. Thanks a lot.