In reply to ben@SystemVerilog.us:
Ben,
thanks again. Would you please explain me this statement?
(!data_valid && src_port==id ##[0:$]src_port!=id)
Does this mean data_valid=0 when src_port==id and then src_port!=id after that until signal_sop happens?
I just need data_valid=0 whenever src_port==id after the signal_eop. Other than that both data_valid and src_port can take any values until signal_sop.
Thanks.