Assertion: Expected data check // A review from a user's question

SystemVerilog
,
7

In reply to ben@SystemVerilog.us:

Hi Ben,

I just tried to compile with Cadence Incisive 15.2 (uses uvm1.1d)
and got a different error now.

irun(64): 15.20-s032: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
Compiling UVM packages (uvm_pkg.sv cdns_uvm_pkg.sv) using uvmhome location /cad/installs/INCISIVE152/tools/methodology/UVM/CDNS-1.1d

	if($rose(go, @(posedge clk))) begin 
	       |

ncvlog: *E,ILLSVF (tb.sv,22|9): Illegal use of sampled value function outside concurrent assertions and procedural blocks.

Any other workarounds ?

Thanks,

David