Assertion: Expected data check // A review from a user's question

Hi Ben,

One last thing is related to the dist function.

I don’t want a back to back 1 on “go” and no back to back 1 on “ready”.

“go” and “ready” should go high for one clock pulse only, never 2 or greater clock cycles consecutively of high.

How to modify the sv code to do this?

Thanks,

David