Assertion: Expected data check // A review from a user's question

SystemVerilog
,
9

Vendor replied with this simple test case.
Their remedy is similar to your fork and join.

//====TESTCASE ============

package om;
reg b;
event a;
endpackage

module top();
import om::*;
reg clk;
task report_period();
    om::b = 1'b1;
    -> om::a;
    @(negedge clk)   //THIS IS CAUSING THE ERROR ncvlog: *E,SFLNOS
    om::b  = 1'b0;
endtask
reg mm2s_err;
property p1;
       @(posedge clk)
                  $rose(mm2s_err) |-> (1'b1, report_period());
       endproperty
assert property(p1);
endmodule

//========TESTCASE ENDS=========

----------------------------------Output:-------------------------------------------
$rose(mm2s_err) |-> (1’b1, report_period());
|
ncvlog: *E,SFLNOS (test_1.sv,18|45): Delays or wait statements in match item task calls are not supported.

You can use following work-around to get away this limitation, using function wrapper to invoke/fork the time-consuming task from within the assertion.

Please refer to the following modified code :

package om;
reg b;
event a;
endpackage

module top();
import om::*;
reg clk;
task report_period();
    om::b = 1'b1;
    -> om::a;
    @(negedge clk)   //THIS IS CAUSING THE ERROR ncvlog: *E,SFLNOS
    om::b  = 1'b0;
endtask

function smi_report_period();
  fork
    report_period();
  join_none
  return 1;
endfunction

reg mm2s_err;
property p1;
  reg ret_val=1;
       @(posedge clk)
                  $rose(mm2s_err) |-> (1'b1, ret_val=smi_report_period()) ##0 ret_val;
endproperty
assert property(p1);

endmodule

This is similar to your fork/join solution.
But your fork/join was not within the function.

Now I need to figure out how to tie this coding workaround into your code.