Accessing module instantiation which has special characters

SystemVerilog
1

Hi All,

I have to call a task from a memory instantiation, “\genblk52.genblk[1].DPS” which is deep in the RTL hierarchy from the test bench. I tried to access by adding "" in front of special characters “\genblk52.genblk[1].DPS” but the questa sim is stopped with error around that.

Can you please help me how to access memory instantiation “\genblk52.genblk[1].DPS” from the test bench?

Thanks
Mahendran

2

In reply to dmahendran:

Its always helpful to include the exact error message or symptom you are seeing. When you say “questa sim is stopped with error around that” it could be a number of things.
But in general the secret to escaped identifiers is it needs to start with the \ and end with a white-space

module lower();

        task say_hello();
                $display("Hello World");
        endtask
endmodule

module upper();
        //lower lower_inst();
        lower \\genblk52.genblk[1].DPS ();
        initial begin
                //upper.lower_inst.say_hello();
                upper.\\genblk52.genblk[1].DPS .say_hello();
        end
endmodule
3

In reply to alexgran:

In reply to dmahendran:
Its always helpful to include the exact error message or symptom you are seeing. When you say “questa sim is stopped with error around that” it could be a number of things.
But in general the secret to escaped identifiers is it needs to start with the \ and end with a white-space

module lower();
task say_hello();
$display("Hello World");
endtask
endmodule
module upper();
//lower lower_inst();
lower \\genblk52.genblk[1].DPS ();
initial begin
//upper.lower_inst.say_hello();
upper.\\genblk52.genblk[1].DPS .say_hello();
end
endmodule

Hi Alex,

Thank you for your reply. but it did not solve my problem. I got the following error after updating my code as per your suggestion.

** Error: (vopt-7052) …/cld_tb_top.sv(1259): Failed to find '\genblk52.DPSRAM_896_69_10 ’ in hierarchical name ‘/a/b/\genblk52.DPSRAM_896_69_10 /zeroMemoryAll’.

Thanks
Mahendran

4

In reply to dmahendran:

Without access to the code in question its hard to say for certain what is going wrong.
I would suggest start by going to the code for instance “/a/b” and looking at the substantiation to make sure its instance name is exactly "\genblk52.DPSRAM_896_69_10 "

5

In reply to alexgran:

Exact instantiations:
It is a gate level simulation.

TSDN16FFPLLSVTA896X69M4SHO \genblk52.DPSRAM_896_69_10 ( .WTSEL({1’b0, 1’b1}),
TSDN16FFPLLSVTA896X69M4SHO \genblk52.genblk1[8].DPSRAM_896_69_10 ( .WTSEL({

Thanks
Mahendran

6

In reply to dmahendran:
It would really help to show the full line of code that is producing the error, and the instances that define then hierarchy. The error message you show has names that were not in your original post

An escaped name in Verilog starts with a singe \ and ends with a space (or any white-space character). You need to do that for each layer in the hierarchy that has an escaped name/

I can only guess, but I’m assuming DPS is the task name you were trying to call. So the example should be

module lower();
        task DIS();
                $display("Hello World");
        endtask
endmodule
 
module upper();
        //lower lower_inst();
        lower \genblk52.genblk[1]();
        initial begin
                //upper.lower_inst.say_hello();
                upper.\genblk52.genblk[1] .DIS();
        end
endmodule

Note the space before .DIS

7

In reply to dmahendran:

Ok, I believe the key thing here is you need to have the same exact thing escaped the same exact way in both the instance name and the hierarchical path.

As Dave says it would really help to have the full code in question. But from the various snippets you’ve included it looks like you have 2 \ characters in your hierarchical reference path (hence that is the syntax I used in my first example.
However in your most recent post it looks like you only have 1 \ character in the instantiation.

Both of these syntaxes are legal. In an escaped identifier you can have any arbitrary characters you want between the leading \ and trailing while-space. Including any number of additional \ characters. The key is just it needs to be the same in every place.

Here is the example updated to use just 1 \


module TSDN16FFPLLSVTA896X69M4SHO();

        task say_hello();
                $display("Hello World");
        endtask
endmodule

module upper();
        //lower lower_inst();
        TSDN16FFPLLSVTA896X69M4SHO \genblk52.DPSRAM_896_69_10 ();
        initial begin
                //upper.lower_inst.say_hello();
                upper.\genblk52.DPSRAM_896_69_10 .say_hello();
        end
endmodule
8

In reply to alexgran:

Hi alex,

I have only one "" infront of genblk52. Now i understood what you have mentioned. I will try and update you.

Thanks
Mahendran

9

In reply to alexgran:

It works now. Thank you Alex and Davis.