Accessing module instantiation which has special characters

SystemVerilog
7

In reply to dmahendran:

Ok, I believe the key thing here is you need to have the same exact thing escaped the same exact way in both the instance name and the hierarchical path.

As Dave says it would really help to have the full code in question. But from the various snippets you’ve included it looks like you have 2 \ characters in your hierarchical reference path (hence that is the syntax I used in my first example.
However in your most recent post it looks like you only have 1 \ character in the instantiation.

Both of these syntaxes are legal. In an escaped identifier you can have any arbitrary characters you want between the leading \ and trailing while-space. Including any number of additional \ characters. The key is just it needs to be the same in every place.

Here is the example updated to use just 1 \


module TSDN16FFPLLSVTA896X69M4SHO();

        task say_hello();
                $display("Hello World");
        endtask
endmodule

module upper();
        //lower lower_inst();
        TSDN16FFPLLSVTA896X69M4SHO \genblk52.DPSRAM_896_69_10 ();
        initial begin
                //upper.lower_inst.say_hello();
                upper.\genblk52.DPSRAM_896_69_10 .say_hello();
        end
endmodule