Accessing module instantiation which has special characters

SystemVerilog
6

In reply to dmahendran:
It would really help to show the full line of code that is producing the error, and the instances that define then hierarchy. The error message you show has names that were not in your original post

An escaped name in Verilog starts with a singe \ and ends with a space (or any white-space character). You need to do that for each layer in the hierarchy that has an escaped name/

I can only guess, but I’m assuming DPS is the task name you were trying to call. So the example should be

module lower();
        task DIS();
                $display("Hello World");
        endtask
endmodule
 
module upper();
        //lower lower_inst();
        lower \genblk52.genblk[1]();
        initial begin
                //upper.lower_inst.say_hello();
                upper.\genblk52.genblk[1] .DIS();
        end
endmodule

Note the space before .DIS