Accessing module instantiation which has special characters

SystemVerilog
3

In reply to alexgran:

In reply to dmahendran:
Its always helpful to include the exact error message or symptom you are seeing. When you say “questa sim is stopped with error around that” it could be a number of things.
But in general the secret to escaped identifiers is it needs to start with the \ and end with a white-space

module lower();
task say_hello();
$display("Hello World");
endtask
endmodule
module upper();
//lower lower_inst();
lower \\genblk52.genblk[1].DPS ();
initial begin
//upper.lower_inst.say_hello();
upper.\\genblk52.genblk[1].DPS .say_hello();
end
endmodule

Hi Alex,

Thank you for your reply. but it did not solve my problem. I got the following error after updating my code as per your suggestion.

** Error: (vopt-7052) …/cld_tb_top.sv(1259): Failed to find '\genblk52.DPSRAM_896_69_10 ’ in hierarchical name ‘/a/b/\genblk52.DPSRAM_896_69_10 /zeroMemoryAll’.

Thanks
Mahendran