Hi,
I need to set a bit which decides which configuration I am in for monitor. and to decide that configuration I need to read a register using reg model.
In my sequence I am able to access reg model but I am not able to use reg model handle in monitor class.
Example code:
**class xyz_seq extends uvm_sequence;
// register with factory
`uvm_object_utils(xyz_seq)
// regmodel handle
xyz_regmodel regmodel;
begin bit[31:0] addr = regmodel.xyz.get_address() ;
regmodel.xyz.read(status, rdata);
$display("Register value (%8x) : %8x", addr, rdata);
end
endclass**
So in the code above, I want to read similar register and decide monitor configuration. How do I achieve it ?
currently I am getting this error in compilation when i use handle as shown below in monitor class?
// regmodel handle
xyz_regmodel regmodel;
Error is :
**Error-[SE] Syntax error
Following verilog source has syntax error :
token ‘xyz_regmodel’ should be a valid type. Please declare it
virtual if it is an Interface.
w6_vout_regmodel regmodel;**
Thank you in advance!
- Dharak. ^