In reply to Dharak Modi:
From where do you set the configuration register you are interested in? You shouldn’t set config db from sequence, as sequence you are starting in run_phase and you want to get the same variable in monitor’s run_phase, so highly chances of monitor’s uvm_config_db get is executed before set statement.
Regarding reg_model in monitor, you can refer: uvm reg read from uvm-monitor | Verification Academy