Access Register read and set bit


I need to set a bit which decides which configuration I am in for monitor. and to decide that configuration I need to read a register using reg model.

In my sequence I am able to access reg model but I am not able to use reg model handle in monitor class.

Example code:

**class xyz_seq extends uvm_sequence;

// register with factory

// regmodel handle
xyz_regmodel regmodel;

begin bit[31:0] addr =            ;, rdata);              
  $display("Register value            (%8x) : %8x", addr, rdata);


So in the code above, I want to read similar register and decide monitor configuration. How do I achieve it ?

currently I am getting this error in compilation when i use handle as shown below in monitor class?
// regmodel handle
xyz_regmodel regmodel;

Error is :
**Error-[SE] Syntax error
Following verilog source has syntax error :
token ‘xyz_regmodel’ should be a valid type. Please declare it
virtual if it is an Interface.

w6_vout_regmodel regmodel;**

Thank you in advance!

  • Dharak. ^

In reply to Dharak Modi:
A Monitor is a passive component, so it’s not a good idea to read register in monitor.

You can get the configuration in a monitor using uvm_config_db.

In reply to bdreku:

Thank you bdreku. So to confirm, I set in uvm_config_db in reg_seq for register read and then get uvm_config_db in uvm_monitor?

In reply to Dharak Modi:
From where do you set the configuration register you are interested in? You shouldn’t set config db from sequence, as sequence you are starting in run_phase and you want to get the same variable in monitor’s run_phase, so highly chances of monitor’s uvm_config_db get is executed before set statement.

Regarding reg_model in monitor, you can refer: uvm reg read from uvm-monitor | Verification Academy

In reply to Dharak Modi:

  1. If you know the configuration before run_phase, then you can use uvm_config_db set with that configuration
  2. Else it’s better to use uvm_event_pool.

In reply to bdreku:

Thank you bdereku, this was helpful.