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  • uvm reg read from uvm-monitor

uvm reg read from uvm-monitor

UVM 5317
dayalan.natarajan
dayalan.natarajan
Full Access
4 posts
September 20, 2016 at 5:36 pm

I am trying to read a UVM Register from run_phase of UVM_Monitor and getting the following error

Error-[IOUCM] Illegal use of class method

dmtcomplex_uvc_pkg, "uvm_pkg::\uvm_reg::read (this.m_dmtcomplex_uvc.m_dmt_reg_block.dmt.dmtint, \this .status, this.intr_occurred, /* path = UVM_DEFAULT_PATH */, /* map = null */, /* parent = null */, /* prior = (-1) */, /* extension = null */, /* fname = "\000" */, /* lineno = 0 */);"
Class methods can't be used in the current context.
Please check LRM for class method usage.

Please let me know if I can call UVM register read or write method from uvm_monitor

Replies

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dhserfer
dhserfer
Full Access
58 posts
September 20, 2016 at 11:00 pm

In reply to dayalan.natarajan:

you can call register reads and writes from any component. You have to set up the reg model correctly and pass the handle to the component. My guess is the register model is not fully set up correctly (either you don't have a handle to the reg model or there is an incorrect setting with respect to the predictor, adapter, sequencer, etc... ). In my opinion, the Monitor is an odd place to perform a front door write.

hmehta
hmehta
Full Access
6 posts
September 21, 2016 at 4:50 am

In reply to dhserfer:

I guess you are right,looks like reg mode is not setup properly and Yes,correct,It's very odd to do front door write in monitor.

xdwzh
xdwzh
Full Access
2 posts
May 30, 2019 at 6:50 pm

In reply to dayalan.natarajan:

have you solved that? I meet the same problem. I am wondering that is it legal to call register in component

chr_sue
chr_sue
Full Access
2914 posts
June 01, 2019 at 12:39 am

In reply to dayalan.natarajan:

Quote:
I am trying to read a UVM Register from run_phase of UVM_Monitor and getting the following error

Error-[IOUCM] Illegal use of class method

dmtcomplex_uvc_pkg, "uvm_pkg::\uvm_reg::read (this.m_dmtcomplex_uvc.m_dmt_reg_block.dmt.dmtint, \this .status, this.intr_occurred, /* path = UVM_DEFAULT_PATH */, /* map = null */, /* parent = null */, /* prior = (-1) */, /* extension = null */, /* fname = "\000" */, /* lineno = 0 */);"
Class methods can't be used in the current context.
Please check LRM for class method usage.

Please let me know if I can call UVM register read or write method from uvm_monitor


The monitor is by intention a passive component, i.e. no activity will be started from this component. This includes also register calls. If you setup your UVM environment correctly you can initiate any register activity through the sequencer/driver. And you can provide any register related data for further processing from the driver.
dhserfer
dhserfer
Full Access
58 posts
June 03, 2019 at 10:25 pm

In reply to xdwzh:

It is possible to call register model methods from components if the component has the reg model handle and the register model is set up correctly.

xdwzh
xdwzh
Full Access
2 posts
June 04, 2019 at 2:28 am

In reply to dhserfer:

You are right. I did find a mistake in my testbench. Thank you!

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 18, 2019 at 4:22 pm

May I ask what is the solution for the TB issue? I am working on a similar case, which is trying to call read_reg inside a BFM which is a uvm_component. But getting same error.

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 12:23 am

In reply to zhehuixu_intel:

I believe you have an architectural problem. Why are you doing simplke things complicated?.
read_reg should be executed always from a sequence and not from a BFM/driver.

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 19, 2019 at 9:38 am

In reply to chr_sue:
The component is more like a controller/host. Which needs to have some knowledge of the registers.
I was trying do to something like this. m_reg_seq.read_reg(register). It is when the compile error pop out. Even encapsulate the read_reg inside the sequence. I won't be able to get the register value out of the sequence.

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 10:36 am

In reply to zhehuixu_intel:

A monitor is a bad place to perform a read. The monitor is a passive component, having only inputs and never initiate something. It is more easy to have a read in the driver or in some other place like a scoreboard.
How do you deal with the register model? Please show some code.

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 19, 2019 at 10:48 am

In reply to chr_sue:

The read_reg was implemented inside the driver/BFM. Not inside the monitor.
Register model wasn't set up by me. But the base register access sequence has instantiated inside the base register sequence.
My question would be what RAL issue might be causing this compilation error.

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 10:54 am

In reply to zhehuixu_intel:

The question is what is 'read_reg'. The access to a register follows this structure:

reg_model_name.reg_map.reg
You should show the piece of monitor code which contains the register access and the accurate compile error.

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 19, 2019 at 11:11 am

In reply to chr_sue:

Here is the code I am trying to use:
rm_base_req = rm_base_seq::type_id::create("rm_base_req"); rm_base_req.read_reg(reg,status,val);
rm_base_seq is extended from uvm_reg_sequence. And this read_reg is the API Provided by the uvm_reg_sequence

read_reg
virtual task read_reg( input uvm_reg rg,
output uvm_status_e status,
output uvm_reg_data_t value,
input uvm_path_e path = UVM_DEFAULT_PATH,
input uvm_reg_map map = null,
input int prior = -1,
input uvm_object extension = null,
input string fname = "",
input int lineno = 0 )
Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 1:01 pm

In reply to zhehuixu_intel:

What are your actual parameters you are using when calling read_reg?

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 19, 2019 at 1:28 pm

In reply to chr_sue:

rm_base_req.read_reg(reg,status,val);
reg: the register inside the reg_model. absolute path to the register inside the reg_model
status:uvm_reg_status
val:32bits wide logic

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 1:58 pm

In reply to zhehuixu_intel:

reg should be something like this: model.regA.
BTW there is no absolute path to the register model becaus ethe reg_model does not belong to the testbench hierarchy.

zhehuixu_intel
zhehuixu_intel
Full Access
6 posts
November 19, 2019 at 2:05 pm

In reply to chr_sue:

I am positive the parameter was passed to the function correctly. Since it has been used at inside sequence.

Just need to some light on how can I use the function inside the uvm_component

chr_sue
chr_sue
Full Access
2914 posts
November 19, 2019 at 11:49 pm

In reply to zhehuixu_intel:

Dou you really pass the reg_model object to the sequence?
You did not show the compile error message so far.

dhserfer
dhserfer
Full Access
58 posts
November 21, 2019 at 2:05 pm

In reply to zhehuixu_intel:

I'm having difficulty understanding your English, so in general, it's best to post your code. I have done something similar to what you are trying, but I didn't use a sequence. I just passed the reg_model handle into the component and used 'peek' (a backdoor read the registers). I don't know if the method I used is 'standard' methodology or not. If you are only doing reads, here is another posting that discusses this:

read the last reply here

chr_sue
chr_sue
Full Access
2914 posts
November 23, 2019 at 1:31 am

In reply to dhserfer:

You can have a reg_model handle in any object including uvm_compnents. A typical example for this approach is a scoreboard which compares values depending on a register content. In this scenario you do not need to perform a backdoor por frontdoor access. Simply perform a get on the register to get the actual content of that register.

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