Xyz.\signal_a[0][0] in the netlist cannot be accessed from testbench due to \

SystemVerilog
1

Hi,

How to access or probe or force a signal in the netlist which has \ preceding it.
The SV testbench cannot recognize .

For example I am trying to access a signal, \signal_a[0][0] in my netlist by forcing:

force xyz_intstance.\signal_a[0][0] =1 ;

This is throwing an error during compile as it cannot detect \signal_a[0][0] .

How do I access this signal correctly?

Thanks

2

In reply to abhi9891:

It would help if you can show the actual error and the way the signal was declared.

Are you trying to access index [0][0] of the signal "\signal_a " or does the escaped name include the "\signal_a[0][0] ". Note in all cases, a space must terminate the escaped name.

3

In reply to dave_59:

I am trying to access “\signal_a[0][0]” which has a \ already due to its declaration.

In the netlist this is declared as
logic \signal_a[0][0];

4

In reply to dave_59:

I have tried accessing the signal by giving "xyz.\signal_a[0][0] " (space added at the end)

I see the compile throws syntax error “.”

Am I missing something?

5

In reply to abhi9891:

As Dave mentioned, it would be very beneficial to post a complete example which demonstrates your issue.

The following code works in all simulators on EDA Playground:


module xyz();
  logic \signal_a[0][0] ;
endmodule

module top;
  xyz i_xyz();
  
  initial begin
    force i_xyz.\signal_a[0][0] = 1'b0;
  end
endmodule
6

In reply to cgales:

Sorry…

It’s actually not working with `define

`define BUS_8 {i_xyz.\signal_a[0][7] ,
i_xyz.\signal_a[0][6] ,
i_xyz.\signal_a[0][5] ,
i_xyz.\signal_a[0][4] ,
i_xyz.\signal_a[0][3] ,
i_xyz.\signal_a[0][2] ,
i_xyz.\signal_a[0][1] ,
i_xyz.\signal_a[0][0] ,
}

7

In reply to abhi9891:

As has been mentioned several times in this thread, it would be very beneficial to post a complete example which demonstrates your issue. Your initial problem statement is completely different from your latest post. It is very difficult to provide assistance without fully understanding the issue.

The following works:


module xyz();
  logic \signal_a[0][0] ;
  logic \signal_a[0][1] ;
  logic \signal_a[0][2] ;
  logic \signal_a[0][3] ;
  logic \signal_a[0][4] ;
  logic \signal_a[0][5] ;
  logic \signal_a[0][6] ;
  logic \signal_a[0][7] ;
endmodule

`define BUS_8 {i_xyz.\signal_a[0][7] ,\
               i_xyz.\signal_a[0][6] ,\
               i_xyz.\signal_a[0][5] ,\
               i_xyz.\signal_a[0][4] ,\
               i_xyz.\signal_a[0][3] ,\
               i_xyz.\signal_a[0][2] ,\
               i_xyz.\signal_a[0][1] ,\
               i_xyz.\signal_a[0][0] }

module top;
  xyz i_xyz();
 
  initial begin
    force `BUS_8 = 8'h00;
  end
endmodule
8

In reply to cgales:

My 2nd problem statement where I mentioned about `define, is the correct one.
Thank you for the response. It worked.