Xyz.\signal_a[0][0] in the netlist cannot be accessed from testbench due to \

SystemVerilog
5

In reply to abhi9891:

As Dave mentioned, it would be very beneficial to post a complete example which demonstrates your issue.

The following code works in all simulators on EDA Playground:


module xyz();
  logic \signal_a[0][0] ;
endmodule

module top;
  xyz i_xyz();
  
  initial begin
    force i_xyz.\signal_a[0][0] = 1'b0;
  end
endmodule