Xyz.\signal_a[0][0] in the netlist cannot be accessed from testbench due to \

SystemVerilog
7

In reply to abhi9891:

As has been mentioned several times in this thread, it would be very beneficial to post a complete example which demonstrates your issue. Your initial problem statement is completely different from your latest post. It is very difficult to provide assistance without fully understanding the issue.

The following works:


module xyz();
  logic \signal_a[0][0] ;
  logic \signal_a[0][1] ;
  logic \signal_a[0][2] ;
  logic \signal_a[0][3] ;
  logic \signal_a[0][4] ;
  logic \signal_a[0][5] ;
  logic \signal_a[0][6] ;
  logic \signal_a[0][7] ;
endmodule

`define BUS_8 {i_xyz.\signal_a[0][7] ,\
               i_xyz.\signal_a[0][6] ,\
               i_xyz.\signal_a[0][5] ,\
               i_xyz.\signal_a[0][4] ,\
               i_xyz.\signal_a[0][3] ,\
               i_xyz.\signal_a[0][2] ,\
               i_xyz.\signal_a[0][1] ,\
               i_xyz.\signal_a[0][0] }

module top;
  xyz i_xyz();
 
  initial begin
    force `BUS_8 = 8'h00;
  end
endmodule