Xyz.\signal_a[0][0] in the netlist cannot be accessed from testbench due to \

SystemVerilog
6

In reply to cgales:

Sorry…

It’s actually not working with `define

`define BUS_8 {i_xyz.\signal_a[0][7] ,
i_xyz.\signal_a[0][6] ,
i_xyz.\signal_a[0][5] ,
i_xyz.\signal_a[0][4] ,
i_xyz.\signal_a[0][3] ,
i_xyz.\signal_a[0][2] ,
i_xyz.\signal_a[0][1] ,
i_xyz.\signal_a[0][0] ,
}