Using Range operator in case statement

SystemVerilog
1

Hi all,

case(val)
    [32'h5:32'h18] : $display("In range");
    default: $dsiplay("DEFAULT");            
  endcase

How can we use range operator inside case statement.

–
Thank you,
mpurna.

2

Hi all,

I got it. We need to use the inside operator along with case statement.

case(val) inside
    [32'h5:32'h18] : $display("In range");
    default: $dsiplay("DEFAULT");            
  endcase

–
Thank you,
mpurna.

3

In reply to mpurna:

Is this synthesizeable?

4

*In reply to rparab:*The
$display statement is not synthesizable. Otherwise, the
case inside statement should be synthesizable if your tool supports. it.

5

In reply to dave_59:

Hi Dave,

I am using inside with a case statement.

For example
logic [3:0] xyz
unique case (xyz) inside
[0:1] : a = 4’d10;
[2:5] : a = 4’d11;
[6:15]: a = 4’d2;
endcase

Two tools gives warnings/error in this case:

  1. Lint gives a warning saying “Case item is not a constant”
  2. LEC HDL Rule Manager gives a warning saying “Partial caase expression in full case statement”

I know it all depends on how these tools interpret it, but, I hope DC doesnt screw it up and interprets it correctly.

Regards,
Rupesh

6

In reply to mpurna:
Hi Dave,

Is it possible to write multiple range which are non contiguous in a single thread. if possible how?

Thanks & Regards,
Saumya

7

In reply to saumyaj:

In reply to mpurna:
Hi Dave,
Is it possible to write multiple range which are non contiguous in a single thread. if possible how?
Thanks & Regards,
Saumyaj


  task disp();
     case(val) inside
      [32'h0:32'h5],[32'h10:32'h20] : $display("RANGE1,RANGE3");
      [32'h6:32'h8] : $display("RANGE2");
      default: $display("DEFAULT");            
    endcase
  endtask
8

In reply to Rahulkumar:

Thanks Rahulkumar:)