Using Range operator in case statement

SystemVerilog
5

In reply to dave_59:

Hi Dave,

I am using inside with a case statement.

For example
logic [3:0] xyz
unique case (xyz) inside
[0:1] : a = 4’d10;
[2:5] : a = 4’d11;
[6:15]: a = 4’d2;
endcase

Two tools gives warnings/error in this case:

  1. Lint gives a warning saying “Case item is not a constant”
  2. LEC HDL Rule Manager gives a warning saying “Partial caase expression in full case statement”

I know it all depends on how these tools interpret it, but, I hope DC doesnt screw it up and interprets it correctly.

Regards,
Rupesh