How to use variable for forcing the path

SystemVerilog
,
1 


task force_bit(input bit [3:0]ramr , input bit [31:0] c_dword); //{ // ramr 0 to 7, c_dword 0 to 4;

    //genvar ramr_loc;
    //ramr_loc = ramr;
   `ifdef ASIC
    //generate
       force <initial_path>.m_65536x156_inst.RAMR[ramr /*ramr_loc*/].V.C[c_dword].A.<inst_name>.Mem[0][1] = 1'b1;
    //endgenerate
    `endif
endtask //}

xmelab: *E,NOTPAR : Illegal operand for constant expression [4(IEEE)].
2

In reply to m_r_m:

use generate block

3

In reply to Jeff_Li_90:
I think we will not be able to use generate block inside the method?

4

In reply to m_r_m:

virtual class abs_intf;
  pure virtual task my_force;
  pure virtual task my_release; 
endclass
    
module tb;

  genvar i;
  logic a[4];   //signal to be forced
  
  
  generate 
    for(i = 0; i < 3; i ++) begin
      class utility_force_release extends abs_intf;
        
        task my_force;
          force tb.a[i] = 1;
        endtask
        
        task my_release;
          release tb.a[i];
        endtask
        
      endclass

      utility_force_release tmp;
      initial begin
        tmp = new();
        my_intf[i] = tmp; // Just for illustration.
        // config_db to uvm side if needed. 
      end
    end
        
  endgenerate
        
 
        function void my_display();
          $display("a[0]:%0h, a[1]:%0h, a[2]:%0h, a[3]:%0h", a[0],a[1],a[2],a[3]);
        endfunction
        
   abs_intf my_intf[4];   
   initial begin
     my_intf[2].my_force;
     my_display();
     
   end
        
endmodule
5

In reply to m_r_m:

or another way if you are using uvm is to go with uvm_hdl_force/release methods, which takes string based paths at run-time. only concern is if you can stand the slowdown.