How to use variable for forcing the path

SystemVerilog
,
4

In reply to m_r_m:

virtual class abs_intf;
  pure virtual task my_force;
  pure virtual task my_release; 
endclass
    
module tb;

  genvar i;
  logic a[4];   //signal to be forced
  
  
  generate 
    for(i = 0; i < 3; i ++) begin
      class utility_force_release extends abs_intf;
        
        task my_force;
          force tb.a[i] = 1;
        endtask
        
        task my_release;
          release tb.a[i];
        endtask
        
      endclass

      utility_force_release tmp;
      initial begin
        tmp = new();
        my_intf[i] = tmp; // Just for illustration.
        // config_db to uvm side if needed. 
      end
    end
        
  endgenerate
        
 
        function void my_display();
          $display("a[0]:%0h, a[1]:%0h, a[2]:%0h, a[3]:%0h", a[0],a[1],a[2],a[3]);
        endfunction
        
   abs_intf my_intf[4];   
   initial begin
     my_intf[2].my_force;
     my_display();
     
   end
        
endmodule