Constraint for address to be inside 4k boundary

SystemVerilog
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1

Hi,

I have address range for 0 to 131072. And for a axi incr burst transfer it should not cross upcoming 4k boundary.
I have given constraint as below but its not working, I still get addresses or lenth or size such that it will cross 4k. Can anyone please tell what is wrong here.

constraint mADDR {mtestADDR inside {[0:131072]};}
constraint mADDRalligned {mtestADDR%16 == 0;}
constraint addr_in_4k { ((mtestADDR%4096) + ((mtestBurstLength + 1) << mtestDataSize)) <= (((int’(mtestADDR/4096))+1)*4096);}

2

In reply to Chandrashekhar Goudar:

The product of number bytes & burst length will give total no. of data transferred in a burst. So we can write a constraint as below.



constraint VALID_BURST_LEN_RANGE {2^Awsize * (Awlen+1) <= 4096;}

Regards,
Shanthi

3

In reply to shanthi:

In my design if address is ~3000 and burst size is 2k, it will throw error as it is crossing 4k address range. Thats why I am considering address also in my constraint.

4

How about something along the lines of:

rand bit [17:0] mtestAddr;
rand bit [17:0] mtestEndAddr;

// I'm not sure exactly the formula to calculate ending address of the burst, but that shouldn't be too hard to figure out with the AXI spec, I'll just guess:
constraint end_addr { mtestEndAddr == mtestADDR + 2^Awsize * Awlen -1; }

// Then the constraint will just make sure that starting and ending address of the burst have bits [17:12] equal which means they are both inside the 4K boundary
constraint addr_in_4k { (mtestADDR[17:12] == mtestEndAddr[17:12];}
5

In reply to Chandrashekhar Goudar:

Please show us declarations for all variables, and an example of values you are getting that should not meet the constraints.

6

In reply to dave_59:

class trans_type;

	rand bit [31:0]                          mtestADDR;
	rand bit [7:0]                          mtestBurstLength;
	rand bit [2:0]                        mtestDataSize;
 	constraint mADDR {mtestADDR inside {[0:131072]};} 
        constraint mADDRalligned {mtestADDR%16  == 0;} 
        constraint addr_in_4k { ((mtestADDR%4096) + ((mtestBurstLength + 1) << mtestDataSize)) <= (((int'(mtestADDR/4096))+1)*4096);}

endclass

Values I get : AWADDR=0x5ba0, AWLEN=0xf3, AWSIZE=0b100
ie:addr=23456, len= 243, size=4(16bytes)
According to my understanding , for address 23456, next 4k boundary is 24576 so we can have 1120 bytes written but 243*16 is 3888 which is crossing it.

7

In reply to Chandrashekhar Goudar:

The problem with your constraint is the
mtestADDR%4096 just gives you the offset into the 4K boundary. You just need

constraint addr_in_4k { mtestADDR%4096 + (mtestBurstLength + 1 << mtestDataSize) <= 4096;}
1 Like
8

In reply to dave_59:

Thanks Dave for pointing out the mistake.

9

In reply to dave_59:

What changes should be made to generate a constraint that won’t cross the 1k boundary for the AHB bus protocol? Given the following variables?

class packet;
  
  rand bit [31:0] Haddr;
  rand bit [2:0]  Hburst;
  rand bit [2:0]  Hsize;
  
endclass
10

In reply to sfenil1804:

I’m not familiar with AHB burst transactions, but for a single burst, the constraint would be

constraint addr_in_1K { Haddr%1024 + 8*(1<<Hsize) <= 1024;}
11

In reply to dave_59:

So we don’t have to consider the burst length (Hburst) for this case?

12

In reply to sfenil1804:

You’ll need to ask someone with AHB expertise.

13

In reply to dave_59:

Hi Dave,
In the code for ahb,Why are we multiplying by 8. I understand you are converting size in bits (Eg: size=2 means 32 bits in this case). However since we are dividing haddr%1024, 1024 is in bytes correct? So shouldn’t hsize be in bytes too?

Shouldn’t it be

constraint addr_in_1K { Haddr%1024 + (1 << Hsize) <= 1024;}

Thanks