Constraint for address to be inside 4k boundary

SystemVerilog
,
6

In reply to dave_59:

class trans_type;

	rand bit [31:0]                          mtestADDR;
	rand bit [7:0]                          mtestBurstLength;
	rand bit [2:0]                        mtestDataSize;
 	constraint mADDR {mtestADDR inside {[0:131072]};} 
        constraint mADDRalligned {mtestADDR%16  == 0;} 
        constraint addr_in_4k { ((mtestADDR%4096) + ((mtestBurstLength + 1) << mtestDataSize)) <= (((int'(mtestADDR/4096))+1)*4096);}

endclass

Values I get : AWADDR=0x5ba0, AWLEN=0xf3, AWSIZE=0b100
ie:addr=23456, len= 243, size=4(16bytes)
According to my understanding , for address 23456, next 4k boundary is 24576 so we can have 1120 bytes written but 243*16 is 3888 which is crossing it.