Constraint for address to be inside 4k boundary

SystemVerilog
,
9

In reply to dave_59:

What changes should be made to generate a constraint that won’t cross the 1k boundary for the AHB bus protocol? Given the following variables?

class packet;
  
  rand bit [31:0] Haddr;
  rand bit [2:0]  Hburst;
  rand bit [2:0]  Hsize;
  
endclass