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assertion macros

SystemVerilog 6739
compilation macro 5 create macros or... 3 generate macro `define 6 #systemverilog #ASSERTION 112
Nimisha Varadkar
Nimisha Varadkar
Full Access
21 posts
October 14, 2020 at 10:07 pm

I'm writing assertion macros and want to pass hierarchical name eg out.vld. But I'm getting an error of illegal location for a hierarchical name while passing it as an argument to the macro `assert_xyz_p(out.vld, in.sel,in.col), Is there a way I can pass hierarchical arguments?

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dave_59
dave_59
Forum Moderator
11263 posts
October 14, 2020 at 10:32 pm

In reply to Nimisha Varadkar:

Macros have no knowledge of SystemVerilog syntax—they just do simple text replacement. You need to make sure to text replaced by the macro is valid syntax.

— Dave Rich, Verification Architect, Siemens EDA

Nimisha Varadkar
Nimisha Varadkar
Full Access
21 posts
October 18, 2020 at 5:27 pm

In reply to dave_59:

Thanks, Dave!

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