I have below code to verify frequency with SVA assertion, but it is failing can you help me here. and ‘clk’ frequency is 2Ghz ,1.998Ghz,2.01Ghz, 1.997Ghz(this is output so freq will change)
Hi ben@SystemVerilog.us,
Thanks for replay, Can you please tell me what is the role of timescale here,
what happen if we use timeprecision as 10fs ?? timeunit 1ps; timeprecision 10fs;
SystemVerilog uses a discrete simulation event model, which means that time is an integer. It will round a real time value to the nearest specified time precision. The smallest time precision it allows is 1 femtosecond (1fs).
The level of precision you are asking for will not work. The literal time value 0.476190476ns is 476190.476fs. With a timeunit 1ps; timeprecision 10fs;, that value gets converted to 476.19ps. The time datatype is a 64-bit integer, so if you were to store this literal in current_time, it would just be 476.
The conclusion I am coming to is that you should be using some other timing analysis tool for this level of accuracy, not discrete event simulation.
This might be an issue with precision of real numbers which only has 56 bits. But you run you r simulation indefinitely so that the 64-bit integer time loses precision when converting to a real number.
Hi Above code working with adding of tolerance. but i want to print current_time value on wave. i have tried with multiple examples but not working. can anyone help me?
module m2b;
timeunit 1ps; timeprecision 100fs;
bit clk, lock=1;
event pass, fail;
time clk_period = 0.5ns
initial forever #250 clk = !clk;
property abc;
time current_time;
disable iff (!lock)
('1,current_time = $realtime ) |=>
((clk_period <= $realtime-(current_time-0.001ns)) &&
(clk_period >= $realtime-(current_time+ 0.001ns)));
endproperty
check1 : assert property(@(posedge clk) abc)
$display(“pass at time %t”, $realtime); else
$display(“fail at time %t”, $realtime);
endmodule
In reply to iamPkumar:
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