In reply to iamPkumar:
SystemVerilog uses a discrete simulation event model, which means that time is an integer. It will round a real time value to the nearest specified time precision. The smallest time precision it allows is 1 femtosecond (1fs).
The level of precision you are asking for will not work. The literal time value 0.476190476ns is 476190.476fs. With a timeunit 1ps; timeprecision 10fs;, that value gets converted to 476.19ps. The time datatype is a 64-bit integer, so if you were to store this literal in current_time, it would just be 476.
The conclusion I am coming to is that you should be using some other timing analysis tool for this level of accuracy, not discrete event simulation.