Frequency_checker

SystemVerilog
2

In reply to iamPkumar:
The following works for me


//`timescale 1ps/10fs
module m2b;
  timeunit 1ps;  timeprecision 100fs;  
  bit clk, lock=1; 
  event pass, fail; 
  initial forever #250 clk = !clk;
  property abc;
    time current_time;
    disable iff (!lock)
        ('1,current_time = $realtime ) |=> 
        ($realtime -current_time == 0.5ns) || 
        ($realtime -current_time == 0.500500501ns) || 
        ($realtime -current_time == 0.499750125ns) || 
        ($realtime -current_time == 0.500751127ns) || 
        ($realtime -current_time == 0.476190476ns);
   endproperty
   check1 : assert property(@(posedge clk) abc) -> pass; else -> fail; 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers: