Passing a ovm_component through set_config_object
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1
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1525
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March 6, 2018
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Wait_for_arbitration_completed not getting activated after sequence_item is arbitrated
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0
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1370
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February 20, 2018
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How to make system call through systemverilog
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4
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15172
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February 16, 2018
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Large Memory footprint assertion
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1
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1906
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January 3, 2018
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Predict function
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1
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2154
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December 5, 2017
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Test Run
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3
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3522
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December 5, 2017
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Callback() Vs Factoryoverride
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2
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8950
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November 23, 2017
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What is the Right & Best way to develop VIP?
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3
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2160
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November 23, 2017
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Is it possible to do a backdoor access using register address and not the register string name?
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1
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1505
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November 14, 2017
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Type casting error in get_config_object
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2
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2060
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November 2, 2017
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Ovm debug message
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2
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1707
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October 24, 2017
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Partial override of a class
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4
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2219
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October 23, 2017
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Why do we need to extend virtual interface wrapper with ovm object
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2
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1812
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October 11, 2017
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Cosimulate SystemVerilog and python
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8
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22871
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October 6, 2017
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Break out of while loop after certain timeout
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4
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3933
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August 1, 2017
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How to handle on-the fly reset scenario in verification component
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1
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2354
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May 31, 2017
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Test Island Concept?
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1
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4349
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April 25, 2017
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How to use set_config with bit[7:0]
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2
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1789
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April 8, 2017
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Set_type_override_by_type
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9
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22314
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April 7, 2017
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Is there a saved name for the sequencer that the sequence related to ? i saw using of m_sequencer this is righ?
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5
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2086
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April 3, 2017
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How to issue ACK sequence on RX sequencer upon getting DATA packet from TX interface?
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2
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2256
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March 21, 2017
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How To Know Which Sequence is Currently Running?
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1
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2192
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March 7, 2017
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How to disable "enable_stop_interrupt" variable in all components of OVM environment?
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0
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1462
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February 26, 2017
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How to Quit the ovm test by looking at specified message and multiple OVM_ERRORS
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1
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1626
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February 10, 2017
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How to debug "Randomization failed" error in Questa
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4
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12006
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February 10, 2017
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Why should connect phase not be top down? Will there be any impact if it is top down. if there will be no impacts why we have not done it in the same way as build phase
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1
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1509
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February 3, 2017
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OVM agent topology for request and response interfaces
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0
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1423
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January 19, 2017
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How to change severity of a message in OVM
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5
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2532
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January 7, 2017
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BUILD PHASE
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3
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3277
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January 2, 2017
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Hierarchial access for DUT signals
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15
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22057
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November 29, 2016
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