Test Run

Hi All,

My question is what happens when we run a test in ovm. which files it access first? what is the order? like it goes through the test file then sequences and all.
can anyone help?
thanks in advance

In reply to nitin273:
Please review the Basic OVM course.

In reply to nitin273:

To understand this, I suggest you to read UVM user guide chapter 17 and Chapter 9 regarding to predefined component classes and UVM common phases. Some high level information listed here. uvm_test will be a good starting point to understand how the uvm test is specified and executed at first.

    17.2 uvm_test
    This class is the virtual base class for the user-defined tests.

The uvm_test virtual class should be used as the base class for user-defined tests. Doing so provides the ability to select which test to execute using the UVM_TESTNAME command line or argument to theuvm_root::run_test task.

For example

prompt> SIM_COMMAND +UVM_TESTNAME=test_bus_retry

The global run_test() task should be specifiedinside an initial block such as

initial run_test();

Multiple tests, identified by their type name, are compiled in and then selected for execution from the command line without need for recompilation. Random seed selection is also available on the command line.

If +UVM_TESTNAME=test_name is specified, then an object of type ‘test_name’ is created by factory and phasing begins. Here, it is presumed that the test will instantiate the test environment, or the test environment will have already been instantiated before the call to run_test().

If the specified test_name cannot be created by the uvm_factory, then a fatal error occurs. If run_test() is called without UVM_TESTNAME being specified, then all components constructed before the call to run_test will be cycled through their simulation phases.

  1. Phasing Overview
    UVM implements an automated mechanism for phasing the execution of the various components in a testbench
    9.6 UVM Common Phases
    The common phases are the set of function and task phases that all uvm_components execute together. All uvm_components are alwayssynchronized with respect to the common phases.

Thankyou for your replies. dave_59 and Lina.Lin