Why does the RAL read() update the mirrored AND desired register model values?

UVM
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Hi,

I have a question about the read() function of register abstraction layer (RAL) of UVM.

From my understanding, when a read() is performed, BOTH the mirror and desired registers are updated by the actual DUT value. I understand why the mirrored value is updated, but why would the desired register be updated?

I think this causes an issue: If I have a case where a DUT bug causes an incorrect register value to be returned on a read. The read mismatches my desired register value and an error is generated by the testbench as expected. However, if I do a second read, no error is detected because the desired register model was updated during the previous read and now matches the DUT value. It also seems like I could even have a race condition where the desired is update before my comparison is done and not see the mismatch.

Can you provide a brief rationale for why the desired register is updated to the dut value? I would expect only the mirrored value to be updated.

Thank you.
Brian

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In reply to BrianK:

It depnds on the register access policy. See this link.

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In reply to dave_59:

Thanks Dave, I think knowing about the “update” functionality helped provide some rationale for it anyway.

I has been thinking the desired value was my ‘predicted’ or expected value, but perhaps that belongs somewhere else in a predictor model? This is my first time using RAL so it’s a little new to me.

Thanks (as always) for your replies and explanations,
Brian