Issue with uvm_hdl_force -> returns 1, but signal is not forced

Hello,

I read about how to use uvm_hdl_force, but I have one big issue - it does not actually force anything.

When i try to use it to force a wire inside the design the function returns 1, but while looking at the waveform the wire never changes.

What am i missing here?

In reply to Azmo:
Try $signal_force to force signal and $signal_release for releasing signal.
Also you need to add -classdebug switch in vsim command.

In reply to Fireblade_uvm:

Hi there,

$signal_force is not recognized, I think it may be ModelSim specific. I am using VCS :(

Then good old force should solve the problem.
i.e force {top.dut.\GENSTS<0>/DFF_OUT/FFX .CE} = 1’b1;

In reply to Azmo:

You should understand what you want to do. There are SV commands to force and release nodes and tool-specific commands.
If you want to be independend from your tool (which is recommended) you can use the force/release assignments.

In reply to Fireblade_uvm:

My problem is that I have to test connectivity for about 100 different wires in a design with 8 different channels - so about 800 signals. Each of this wires could propagate to an output pin via a series of muxes, which I can control from the tb. So my plan is as follows:

  1. Force X on all relevant wires
  2. Select 1 wire
  3. Set up muxes to drive that wire to output pin
  4. Force random value on the wire
  5. Compare output pin to forced value
  6. Return wire to X and move on to next wire

If I use force this means I have to have all these written down before compile happens. Since there are so many of them a Perl script + regular force from an interface is currently my B option.

What i tried to do is setup all the paths into an array, loop through the array and force - check - release each signal. The function would have been perfect, but sadly it didn’t work.

In reply to Azmo:

I suggest that you identify groups of signals instead driving each signal alone and also use for loops for this 8 different channels.

In reply to Fireblade_uvm:

Thanks for the input, this is exactly what I planned to do - split the 8 channels in 8 different interfaces and write them down via macros…

Thankfully we resolved the issue with uvm_hdl_force internally - had to run the test in debug mode - so that’s working fine now.