You should understand what you want to do. There are SV commands to force and release nodes and tool-specific commands.
If you want to be independend from your tool (which is recommended) you can use the force/release assignments.
My problem is that I have to test connectivity for about 100 different wires in a design with 8 different channels - so about 800 signals. Each of this wires could propagate to an output pin via a series of muxes, which I can control from the tb. So my plan is as follows:
Force X on all relevant wires
Select 1 wire
Set up muxes to drive that wire to output pin
Force random value on the wire
Compare output pin to forced value
Return wire to X and move on to next wire
If I use force this means I have to have all these written down before compile happens. Since there are so many of them a Perl script + regular force from an interface is currently my B option.
What i tried to do is setup all the paths into an array, loop through the array and force - check - release each signal. The function would have been perfect, but sadly it didn’t work.