Issue with uvm_hdl_force -> returns 1, but signal is not forced

In reply to Fireblade_uvm:

My problem is that I have to test connectivity for about 100 different wires in a design with 8 different channels - so about 800 signals. Each of this wires could propagate to an output pin via a series of muxes, which I can control from the tb. So my plan is as follows:

  1. Force X on all relevant wires
  2. Select 1 wire
  3. Set up muxes to drive that wire to output pin
  4. Force random value on the wire
  5. Compare output pin to forced value
  6. Return wire to X and move on to next wire

If I use force this means I have to have all these written down before compile happens. Since there are so many of them a Perl script + regular force from an interface is currently my B option.

What i tried to do is setup all the paths into an array, loop through the array and force - check - release each signal. The function would have been perfect, but sadly it didn’t work.