Interview Questions on UVM

UVM
,
1

I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries:

  1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro?
  2. For debugging purpose, how to print messages that indicates the components phase?
  3. How to use set_config_* for setting variables of sequence?
  4. How to fill the gap b/w different objections?
  5. How multiple set_config_* are resolved at same hierarchy level and at different hierarchy level?
  6. Is it possible to connect multiple drivers to one sequencers ? if yes, then how?
  7. What is the disadvantage if sequence is registered to sequencer using utility macros? If sequence is not registered with sequencer, then how to invoke the sequence execution?
2

In reply to Subbi Reddy:

I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries:

  1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro?
  2. For debugging purpose, how to print messages that indicates the components phase?
  3. How to use set_config_* for setting variables of sequence?
  4. How to fill the gap b/w different objections?
  5. How multiple set_config_* are resolved at same hierarchy level and at different hierarchy level?
  6. Is it possible to connect multiple drivers to one sequencers ? if yes, then how?
  7. What is the disadvantage if sequence is registered to sequencer using utility macros? If sequence is not registered with sequencer, then how to invoke the sequence execution?

Please help me anyone

3

1 &7 .The `uvm_seuqence_utils(sequencer) was used to register seq to sequencer .This method is deprecated.Drawback is that it hinders re usability and never works for parametrized sequences.


2. phase.get_name()

3.+uvm_set_config* is used to set the configuration value from the command line processor.
Eg ;- +uvm_set_config_int=uvm_test_top.soc_env,mode,5

4.The gap between objections , time between a raise and drop ? it depends on the code following the raise_objection

5.Highest hierarchy wins , when used within build_phase.

6.No sequencer to driver is a one to one connection.

Hope this helps ,if you have more questions pl do post them.

4

In reply to bl4ckp3rl :
Thank you for responding and also please respond for the below Queries?

  1. How to send different sequences frequently for same interface?
  2. How to send different sequence_items frequently for same driver
  3. How to test 4MB Memory without effect the simulation(halt or stop)?
5

In reply to Subbi Reddy:

  1. You do not send sequences and you do not send them to an interface.
  2. The common way is to use a loop with a certain number of cycles. We do not send the seq_items to the driver in the common way. The driver is pulling them from the sequencer.
  3. You can write/read to a certain number of addresses. write data can be stored in an assiciative array and can be compared with the corresponding read value from the DUT.
6

In reply to chr_sue:

  1. How to send different sequence_items frequently for same driver
    correction of the Query: 1. The Driver need to get different sequence_items from different sequences under same sequencer
    2. can we use sequence library for this scenario?? At what scenario we can use Sequence library?

  2. You can write/read to a certain number of addresses. write data can be stored in an associative array and can be compared with the corresponding read value from the DUT.
    correction of the Query: The requirement is each memory address need to check for read and write