I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries:
- don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro?
- For debugging purpose, how to print messages that indicates the components phase?
- How to use set_config_* for setting variables of sequence?
- How to fill the gap b/w different objections?
- How multiple set_config_* are resolved at same hierarchy level and at different hierarchy level?
- Is it possible to connect multiple drivers to one sequencers ? if yes, then how?
- What is the disadvantage if sequence is registered to sequencer using utility macros? If sequence is not registered with sequencer, then how to invoke the sequence execution?
1 &7 .The `uvm_seuqence_utils(sequencer) was used to register seq to sequencer .This method is deprecated.Drawback is that it hinders re usability and never works for parametrized sequences.
2. phase.get_name()
3.+uvm_set_config* is used to set the configuration value from the command line processor.
Eg ;- +uvm_set_config_int=uvm_test_top.soc_env,mode,5
4.The gap between objections , time between a raise and drop ? it depends on the code following the raise_objection
5.Highest hierarchy wins , when used within build_phase.
6.No sequencer to driver is a one to one connection.
Hope this helps ,if you have more questions pl do post them.
In reply to bl4ckp3rl :
Thank you for responding and also please respond for the below Queries?
- How to send different sequences frequently for same interface?
- How to send different sequence_items frequently for same driver
- How to test 4MB Memory without effect the simulation(halt or stop)?