Hello guys, I have question regarding the verification process of an Interface protocol.
In the past, I had made a FIFO, verified it using Random Stimulus, Directed Tests to cover/verify suspicious areas of the design.
Made two versions one using SVTB, and one using UVM.
I have no experience in verifying protocols at all, I don’t know where to start. Is there any material on web that discusses verification of interfaces or an ebook?
For a Module/Design it’s pretty straight forward if it’s not connected to an interface. however in real-life, designs always have a specific interface which we must abide by its rules.
Thank you! :)
In reply to haithamx15:
Verification is always related to the interface, because you are stimulating your design through the interface. Also a FIFO has an inreface,even it is pretty simple.
And a module/design has always an interface.
All interfaces require a special protocol, some of them have a very simple one and others a very complicated. The way to stimulate them is always the same. It is done from the drivers run_phase.
In reply to chr_sue:
What determines what the driver should drive?
Assume that I have two agents, master and slave and an interface in between.
Master sends a request, I receive it monitor, and subsquently drive the appropriate response. My question here. what determines what should be random? response shouldn’t be random. however what are the attributes that should be randomized?
For examlple, assume a read request, should the slave be randomized to emulate a real life behaviour of a memory for example? where it might be busy, or slow, or fetching some info from another chip for exampe. should this be randomized?
In reply to haithamx15:
THe driver has to implement the bus protocol. It generates all control signals and data/addr signals with the right timing.
In case of a response the response itself is not rando, but some data might be random.
In reply to chr_sue:
In reply to haithamx15:
THe driver has to implement the bus protocol. It generates all control signals and data/addr signals with the right timing.
In case of a response the response itself is not rando, but some data might be random.
Let’s assume I wanna check how protocol behaves when it is busy, for example… I send a read command to slave, assume slave captures the request however, it needs to fetch it from other place, hence more cycles will elapse until the master receives a response from slave and with that response is the data requested. My question is, how can I emulate such behavior in slave. this behavior is from real life chips/ic’s, and that is why I asked should I make it random the response. I wanna test how, the protocol will behave in this case in order to check if it functions correctly.
In reply to haithamx15:
You have to implement the slave behavior in your UVM testbench. Finally this is a driver reacting on a request.