In reply to haithamx15:
Verification is always related to the interface, because you are stimulating your design through the interface. Also a FIFO has an inreface,even it is pretty simple.
And a module/design has always an interface.
All interfaces require a special protocol, some of them have a very simple one and others a very complicated. The way to stimulate them is always the same. It is done from the drivers run_phase.