Connect DUT signals to interface signal problem in virtual interface limitation

UVM
,
1

Dear all

I’m trying to understand virtual interface and uvm_config_db, so I make a simple example

As I seen before in Mentor community, Virtual interface has limitation.
Virtual interface can only write to register(logic) variables.
Not net(wire) types.

but in my example DUT has one output.
at this time, How do I write date and get result data from DUT?
the problem is that can I use output in interface implementation?
I’m struggling on my example code.
Actually I’d like to set by uvm_config_db with virtual interface then somewhere I will get the variable by uvm_config_db so I’ll trying to set a and b data and want to receive output data.
I thought that is very simple but still struggling.

Could you help me for understanding?

2

In reply to UVM_LOVE:

There is no limitation with respect to the SV interface construct. It might have variables like logic and nets (wires). Wires are only needed in case of inouts. outputs can be of type logic.
But in your example the interface construct tis wrong. It should be like this:

interface my_interface();
  logic [31:0] a;
  logic [31:0] b;
  logic [31:0] c;  
endinterface

Unfortunately I do not see how your DUT ports are looking like.

3

In reply to chr_sue:

In reply to UVM_LOVE:
There is no limitation with respect to the SV interface construct. It might have variables like logic and nets (wires). Wires are only needed in case of inouts. outputs can be of type logic.
But in your example the interface construct tis wrong. It should be like this:

interface my_interface();
logic [31:0] a;
logic [31:0] b;
logic [31:0] c;  
endinterface

Unfortunately I do not see how your DUT ports are looking like.

Even I modified as your recommend, I’ve got Expreesion connected to an ‘inout’ port must be collapsible.
Do I need to set as inout like this?

4

In reply to UVM_LOVE:

I do not see any inout port in your code. And as I said if you want connect to an inout you have to declare a wire in your interface for exactly this signal. The SV interface itself does not define the data direction. This will be done by the moports. But the modports are an option.

5

In reply to chr_sue:

.c(sub.c)
c has the same error about Expression connected to an ‘inout’ port must be collapsible.

Does this mean, c has to be declared inout?

6

In reply to UVM_LOVE:

You have a couple of weaknesses in your testbench/design.
This link is running, but you do not have declared the seq_item, a sequence and the sequencer.

7

In reply to chr_sue:

In reply to UVM_LOVE:
You have a couple of weaknesses in your testbench/design.
This link is running, but you do not have declared the seq_item, a sequence and the sequencer.
llegal location for a virtual interface versio(1) - EDA Playground

Sorry , It seems running but the value of a is 0.
Actually the purpose of this example is to control the variable of virtual interface

    my_intf.a =7;
    my_intf.b =6;
    c = my_intf.c;
    

    $display("the value of a is %0d",c);

As you can see the above code, it should be a 13 not 0.
That means this virtual interface doesn’t control the DUT.

8

In reply to UVM_LOVE:

I was adding a few uvm_info into the driver.
The problem might be caused gy your dirty UVM environment.
See here:

9

In reply to chr_sue:

In reply to UVM_LOVE:
I was adding a few uvm_info into the driver.
The problem might be caused gy your dirty UVM environment.
See here:
llegal location for a virtual interface versio(1) - EDA Playground

Thanks but Actually I want to use DUT’s hierarchical nameing path into the virtual interface like this

  my_interface intf(
    .a(sub.a),
    .b(sub.b),
    .c(sub.c)
  );

not

  sub DUT(
    .a(intf.a),
    .b(intf.b),
    .c(intf.c)
  );
10

In reply to UVM_LOVE:

Your problem is in the driver. It is a timing issue. See here add.sv:

11

In reply to chr_sue:

In reply to UVM_LOVE:
Your problem is in the driver. It is a timing issue. See here add.sv:
llegal location for a virtual interface versio(1) - EDA Playground

Yes I realized it.
But what baffles me is that the result difference by Tools.
You can find out if you run with VCS, then no need to #2.

Anyway,

Isn’t possible way to use like this?

my_interface intf( .a(sub.a), .b(sub.b), .c(sub.c) ); not intf.x?

12

In reply to UVM_LOVE:

When I say timing I mean with respect to the SV scheduler. This describes the behavior in a timeslot. I see VCS is running without the additional delay between the input and the output assignment. I’m not sure if this meets the SV requirements.
Only VCS is accepting this. Questa, Incisive and Reviera do not accept this.

With respect to the connection of your interface. The intention of the interface is to connect components/modules together, i.e. in 1 block a signal is an input and in another one the same signal is an output. This does not fit with your interface definition.