I’m trying to understand virtual interface and uvm_config_db, so I make a simple example
As I seen before in Mentor community, Virtual interface has limitation.
Virtual interface can only write to register(logic) variables.
Not net(wire) types.
but in my example DUT has one output.
at this time, How do I write date and get result data from DUT?
the problem is that can I use output in interface implementation?
I’m struggling on my example code.
Actually I’d like to set by uvm_config_db with virtual interface then somewhere I will get the variable by uvm_config_db so I’ll trying to set a and b data and want to receive output data.
I thought that is very simple but still struggling.
There is no limitation with respect to the SV interface construct. It might have variables like logic and nets (wires). Wires are only needed in case of inouts. outputs can be of type logic.
But in your example the interface construct tis wrong. It should be like this:
In reply to UVM_LOVE:
There is no limitation with respect to the SV interface construct. It might have variables like logic and nets (wires). Wires are only needed in case of inouts. outputs can be of type logic.
But in your example the interface construct tis wrong. It should be like this:
I do not see any inout port in your code. And as I said if you want connect to an inout you have to declare a wire in your interface for exactly this signal. The SV interface itself does not define the data direction. This will be done by the moports. But the modports are an option.
You have a couple of weaknesses in your testbench/design.
This link is running, but you do not have declared the seq_item, a sequence and the sequencer.
When I say timing I mean with respect to the SV scheduler. This describes the behavior in a timeslot. I see VCS is running without the additional delay between the input and the output assignment. I’m not sure if this meets the SV requirements.
Only VCS is accepting this. Questa, Incisive and Reviera do not accept this.
With respect to the connection of your interface. The intention of the interface is to connect components/modules together, i.e. in 1 block a signal is an input and in another one the same signal is an output. This does not fit with your interface definition.