In reply to chr_sue:
In reply to UVM_LOVE:
There is no limitation with respect to the SV interface construct. It might have variables like logic and nets (wires). Wires are only needed in case of inouts. outputs can be of type logic.
But in your example the interface construct tis wrong. It should be like this:
interface my_interface();
logic [31:0] a;
logic [31:0] b;
logic [31:0] c;
endinterface
Unfortunately I do not see how your DUT ports are looking like.
Even I modified as your recommend, I’ve got Expreesion connected to an ‘inout’ port must be collapsible.
Do I need to set as inout like this?