Writing a sequence within a sequence

SystemVerilog
, ,
3

In reply to ak180:
Changed your code.


module m;
    `include "uvm_macros.svh"   import uvm_pkg::*;
    bit clk, busy, valid; 
    /* busy ___|-------------|_____
       valid _____|-------|________ */
    /* sequence seq_busy;
        $rose(busy) ##[1:$] $fell(busy);
    endsequence
     
    sequence seq_valid;
        $rose(valid) ##[1:$] $fell(valid);
    endsequence */ 
    initial forever #10 clk = !clk;

    ap_busy_valid: assert property (@(posedge clk)
         $rose(busy)  |-> ##1  // is ##1 Needed?? Depends on requirements 
           $rose(valid)[->1] ##1 $fell(valid)[->1] intersect  $fell(busy)[=1] );

     initial begin
            repeat (90) begin
              @(posedge clk); #2; 
              if (!randomize(busy, valid) with {
               busy  dist {1'b1 := 8, 1'b0 := 1};
               valid dist {1'b1 := 1, 1'b0 := 1}; 
              }) `uvm_error("MYERR", "This is a randomize error"); 
            end
            $finish;
          end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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