Write an assertion ,after the clk has arrived within 5 clk cycles write or read should not occur

SystemVerilog
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In reply to SUNODH:
Since this is a homework question, I’ll give guidelines into the solutions.

I’m writing an assertion to check at the initial stage of clk my read & write should not happen until 5 clk cycles.

One of the main requirements is “at the initial stage of clk”.
That is not well defined, but it typically means during the forst “n” clock after boot.
Assuming n==10, you could use an initial statement with a loop for 10 clocking events.
There you can write a concurrent or an immidiate assertion.

I written as below


sequence w_r
##[1:5] (read & write )
endsequence
sequence not_w_r
not w_r
endsequence
assert property (@posedge clk) first_match not_w_r else $display("----- assertion failed -----");

the not is aproperty operator. You need to understand what first_match is and where it is used. See my papers to get a good understanding of assertions.

Here I have 2 doubts:

  1. can i write w_r sequence without any event or clk semantics

Yes, as long as you do not use an endpoint when tht sequence is used.

  1. Is my understanding is correct for not w_r : It means my sequence w_r should not happen, if w_r seq occurred my assertion will show fail

Yes

Actually, we can write it simply like below

 
@(posedge clk) $rose(clk) |-> ##[0:5] ((!write) || (!read));

NO, you do not want to do that with a rose of the clock. $rose is used with a module variable.

Links to my papers are in my signature below.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
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    Understanding the SVA Engine,
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    Reflections on Users’ Experiences with SVA, part 1
    Reflections on Users’ Experiences with SVA
    Reflections on Users’ Experiences with SVA, part 2
    Reflections on Users’ Experiences with SVA, Part II
    Understanding and Using Immediate Assertions
    Understanding and Using Immediate Assertions
    SUPPORT LOGIC AND THE ALWAYS PROPERTY
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    SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
    SVA in a UVM Class-based Environment
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    SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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